Featues• Supescala IEEE Floating-Point-Pocesso• Off-Chip Havad Achitectue Maximizes Signal Pocessing Pefomance• 50 ns, 20 MIPS Instuction Rate, Single Cycle Execution• 60 MFLOPS Peak, 40 MFLOPS Sustained Pefomance• 1024-Point Complex FFT Benchmak: 0.975 ms• Divide (y/x): 300 ns• Invese Squae Root (1/ /x): 450 ns• 32-bit Single-Pecision and 40-bit Extended-Pecision IEEE Floating-Point DataFomats• 32-bit Fixed-Point Fomats, Intege and Factional, with 80-bit Accumulatos• IEEE Exception Handling with Inteupt on Exception• Thee Independent Computation Units: Multiplie, ALU, and Bael Shifte• Dual Data Addess Geneatos with Indiect, Immediate, Modulo, and Bit ReveseAddessing Modes• Two Off-Chip Memoy Tansfes in Paallel with Instuction Fetch and Single-CycleMultiply and ALU Opeations• Multiply with Add and Subtact fo FFT Buttefly Computation• Efficient Pogam Sequencing with Zeo Ovehead Looping: Single-Cycle Loop Setup• Single-Cycle Registe File Context Switch• 23ns Extenal RAM Access Time fo Zeo-Wait-State, 40 ns Instuction Execution• IEEE JTAG Standad 1149.1 Test Access Pot and On-chip Emulation Cicuity• 223 CPGA package fo beadboading• 256 Multi-laye Quad Flat Pack, Flat Leads, Fo Flight Models• Fully compatible with Analog Devices ADSP-21020• No Single Event Latch-up below a LET Theshold of 80 MeV/mg/cm2• Tested up to a Total Dose of 100 kads (Si) accoding to MIL STD 883 Method 1019• SEU Eo Note in GEO Obit Bette than 5E-7 Eo/Device/Day (wost case)• Fo 25 MHz Specification, Contact Atmel fo Availability• Quality Gades - ESCC with 9512/002 and QML-Q o V with 5962-99539
