FPGA configuation seial EEPROM poviding an easy-to-use, cost-effective configuation memoy fo FPGAs. It comes packaged in a 28-pin 400-mils wide FP package. A simple seial-access pocedue configues one o moe FPGA devices via the configuato. The use can select the polaity of the eset function by pogamming fou EEPROM bytes. The device suppots a wite-potection mechanism within its pogamming mode.
Featues• EE Pogammable 1,048,576 x 1-bit Seial Memoy Designed to Stoe ConfiguationPogams fo Field Pogammable Gate Aays (FPGAs)• Vey Low-powe CMOS EEPROM Pocess• In-System Pogammable (ISP) via Two-Wie Bus• Simple Inteface to SRAM FPGAs• Compatible with AT40K Devices• Cascadable Read-back to Suppot Additional Configuations o Highe-density Aays• Pogammable Reset Polaity• Low-powe Standby Mode• High-eliability– Enduance: 5,104Read Cycles– Data Retention: 10 Yeas• No Single Event Latch-up below a LET Theshold of 80 MeV/mg/cm2@125°C• Tested up to a Total Dose of (accoding to MIL STD 883 Method 1019)– 20 kads (Si) Read-only mode when Biased– 60 kads (Si) Read-only mode when Unbiased• Opeating Range: 3.0V to 3.6V, -55°C to +125°C• Available in 400 mils Wide 28 Pins DIL Flat Pack
1 Mbit AT17LV010-10DP-E 28-pin Flat Pack Engineeing Samples1 Mbit AT17LV010-10DP-MQ 28-pin Flat Pack Militay Level B1 Mbit AT17LV010-10DP-SV 28-pin Flat Pack Space Level B
